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Schuyler Eldridge

Login: seldridge

Company: @IBM

Location: Yorktown Heights, NY

Bio: Postdoc. Chisel/FIRRTL hardware design. RISC-V. PhD from @bu-icsg.

Blog: seldridge.github.io

Member of

Repositories

algorithms: Software engineering practice, algorithms, and data structures
carrv.github.io: Workshop on Computer Architecture Research with RISC-V (CARRV)
cbs_radio: CBS Radio Downloader
chisel: null
chisel2-base: Base build environment for Chisel projects
chisel3: new firrtl based chisel
chisel3-base: Bare-bones Chisel 3 project
cocktails: Cocktail Menu
CSS_Final_Project: Computational Social Science Final Project
cv-simple: A simple CV with open source metric macros
dana: Neural Networks should be Functional Primitives or: a neural network accelerator for RISC-V microprocessors
docker-texlive: Full TeX Live
dotfiles: configuration dump
fann: Official github repository for Fast Artificial Neural Network Library (FANN)
firrtl: Flexible Intermediate Representation for RTL
firrtl-issue-764-test: https://github.com/freechipsproject/firrtl/issues/764#issuecomment-374680652
fpga-zynq: Support for Rocket Chip on Zynq FPGAs
generator-bootcamp: Generator Bootcamp Material: Learn Chisel the Right Way
hdl-scripts: Dumping ground for HDL-related scripts I use or find useful
iverilog: Icarus Verilog
jappavoo.github.com: Jonathan Appavoo Home Page
linguist: Language Savant
make-markdown: Markdown Automation
melpa: Recipes and build machinery for the biggest Emacs package repo
menus: Repository of food and drink menus created over the years
palette-art: Experiments in color
project-template: null
resume: LaTeX resume
riscv-boom-doc: Documentation for the BOOM processor
riscv-fesvr: RISC-V Frontend Server
riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC 5.3.0
riscv-isa-manual: RISC-V Instruction Set Manual
riscv-isa-sim: Spike, a RISC-V ISA Simulator
riscv-pk: RISC-V Proxy Kernel
riscv-tools: RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
rocket: Rocket Microarchitectural Implementation of RISC-V ISA
rocket-chip: Rocket Chip Generator
rocket-rocc-examples: Tests for example Rocket Custom Coprocessors
sage-ski: Repository for BU SAGE Ski Trips
seldridge.github.io: Personal website:
travis-parallel-test: null
treadle: Chisel/Firrtl execution engine
ulysses: The Great Tactician (of computing intercollegiate figure skating results)
verilog: Repository for basic (and not so basic) Verilog blocks with high re-use potential
verilog_tex: Document and example code for introductory (and not so introductory) Verilog

Commits To

Repository	Most Recent Commit	# Commits

This work is supported by the National Institutes of Health's National Center for Advancing Translational Sciences, Grant Number U24TR002306. This work is solely the responsibility of the creators and does not necessarily represent the official views of the National Institutes of Health.