Juniper/open-register-design-tool

Name: open-register-design-tool

Owner: Juniper Networks

Description: Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Created: 2016-06-14 18:33:32.0

Updated: 2018-03-28 19:34:31.0

Pushed: 2018-03-28 19:34:30.0

Homepage:

Size: 6356

Language: Verilog

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README

open-register-design-tool

Ordt is a tool for automation of IC register definition and documentation. It currently supports 2 input formats:

1. SystemRDL - a stardard register description format released by Accellera.org
2. JSpec - a register description format used within Juniper Networks

The tool can generate several outputs from SystemRDL or JSpec, including:

• SystemVerilog/Verilog RTL code description of registers
• UVM model of the registers
• C++ models of the registers
• XML and text file register descriptions
• SystemRDL and JSpec (conversion)

Easiest way to get started with ordt is to download a runnable jar from the release area.
Ordt documentation can be found here.